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Position: Senior CAD Engineer (San Jose, CA) 

Job Overview:
We are seeking a highly skilled Senior CAD Engineer to support advanced semiconductor design and verification environments across leading-edge technology nodes. This role will be responsible for PDK enablement, CAD flow development, and layout validation, with a strong focus on ensuring robust, scalable, and high-quality design infrastructure for successful tapeouts.

The ideal candidate brings deep expertise in CAD tools, semiconductor processes, and physical verification, along with a strong problem-solving mindset and the ability to collaborate across design and engineering teams.

This is a W2 contract position and is not eligible for C2C or W2 referral candidates.

Key Responsibilities: 
• Perform PDK installation, configuration, and validation for advanced technology nodes (e.g., 4nm, 2nm and beyond)
• Develop, implement, and maintain CAD flows and design environments, including:
o Cadence Virtuoso
o Calibre DRC/LVS
o Cadence EMX and Quantus
• Support top-level layout and sub-cell development, ensuring design integrity and compliance
• Interpret, analyze, and debug layout and verification issues across multiple design stages
• Execute and optimize parasitic extraction and physical verification flows
• Collaborate with cross-functional teams (design, layout, verification) to improve flow efficiency and quality of results (QoR)
• Ensure readiness and reliability of CAD infrastructure for advanced node tapeouts
• Develop automation, checks, and methodologies to improve design productivity and accuracy

• Master’s degree in Electrical Engineering, Physics, or a related field (equivalent combination of education and relevant industry experience will be considered)
• Minimum 7+ years of experience in CAD engineering with direct involvement in advanced node tapeouts
• Strong experience with parasitic extraction and verification tools, such as:
o Cadence Quantus / QuantusFS
o Calibre xRC / xACT / xACT3D
• Hands-on knowledge of Calibre LVS and DRC flows and rule decks
• Experience with 3D field solvers, such as:
o Cadence EMX
o Ansys HFSS
• Solid understanding of:
o Semiconductor technology and fabrication processes
o Semiconductor device physics
o Process modeling and mask layout concepts
• Familiarity with BEOL and FEOL process architectures, including:
o Planar
o FD-SOI
o FinFET
o Gate-All-Around (GAA)
• Strong analytical and problem-solving skills with exceptional attention to detail
• Excellent written and verbal communication skills with the ability to work effectively in team environments
• Self-motivated with a continuous improvement and growth mindset

• Proven track record of supporting multiple technology nodes and complex tapeouts
• Experience enhancing CAD flows through automation and scripting

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Hours you will be work as a Senior CAD Engineer: First shift (8am-5pm), Monday through Friday

Compensation you will receive as a Senior CAD Engineer: $100-$120 per hour 

Saige Partners, one of the fastest growing technology and talent companies in the Midwest, believes in people with a passion to help them succeed. We are in the business of helping professionals Build Careers, Not Jobs. Saige Partners believes employees are the most valuable asset to building a thriving and successful company culture, which is why we offer a benefit package and convenient weekly payment solutions that helps our employees stay healthy and maintain a positive work/life balance. Contact us to learn more about the opportunity below or check out other opportunities at https://careers.saigepartners.com/.